Full Custom VLSI Design

Dr. Ryan Gerdes,Electrical and Computer Engineering, Utah State University


Our design projects will be fabricated using the AMI C5F/N Process. This is a 0.6um (lambda=0.3um) 2 poly, 3 metal process. We will use the SCMOS_SUBM rules. For details see The Mosis Website.


We will be using a tool suite from Cadence Design Systems called Front to Back Design Environment 5.1.41 and hereafter just referred to as "Cadence". The first thing to do is to get Cadence set-up on your account by following the Install Guide. Next you will want to learn the basics of Cadence by following the Cadence Tutorial.