Nanometer VLSI Design (Graduate course)

Course description:

Semiconductor industry has evolved rapidly over the past four decades to meet the increasing demand on computing power by continuous miniaturization of devices. Now we are in the nanometer technology regime with the device dimensions scaled below 100nm. VLSI design using nanometer technologies involves some major challenges. This course will explain all the major challenges associated with nanoscale VLSI design such as dynamic and leakage power, parameter variations, reliability and robustness. The course will present modeling and analysis techniques for timing, power and noise in nanometer era. Finally, the course will cover the circuit/architecture level design solutions for low power, high-performance, testable and robust VLSI system. The techniques will be applicable to design of microprocessor, digital signal processor (DSP) as well as application specific integrated circuits (ASIC). The course includes a project which requires the student to work on a nanometer design issue. Recommended preparation: VLSI Systems (EECS 426) or MOS Integrated Circuit Design (EECS 485).