Hardware Platform

Welcome to Hardware Platform webpage!

The goal for this effort is to provide researchers and practitioners from academia and industry with tools and common hardware platform to perform various experimental analyses. The platforms we develop can help with hardware Trojan detection, side-channel attacks analysis, vulnerability analysis, etc. They include FPGA-Based platforms, ASIC platforms and WARP platforms.

FGPA

HARDWARE TROJAN INSERTION ON FPGA

Download the article in PDF and additional supplementary file

This article introduces methods to insert different types of hardware Trojans into Xilinx FPGAs in a step by step manner. These infected FPGAs can be used for hardware Trojan related investigations and research. The topics included are Trojan insertion methods for targeting techniques for full activation, power-based, and delay-based detection, respectively.

This article assumes the reader has basic knowledge of HDL and some experience with FPGA design

ASIC

ASIC DATA COLLECTION USING FPGA INTERFACE

Download the article in PDF and additional supplementary file.

The article will detail an experiment setup to quickly collect data from application specific integrated circuit (ASIC) test chips. The topics covered are Serial UART communication for field programmable gate array (FPGA), Linux serial communication, VHDCI and VmodBB wiring and FPGA Programming. FPGA programming includes Controller Design, FPGA clock manipulation, UART communication module and VHDC usage.

This article assumes the reader has basic knowledge of VHDL and some experience with either Bash or Python.

WARP

HARDWARE TROJAN INSERTION ON WARP

Download the article in MP4.

This video describes a step by step process to introduce a trojan into a WARP v1 board. Familiarity with a hardware description language and Matlab is assumed.

The framework for WARP is complex, and the various steps outlined will help to make it easier to use it. The main steps outlined are the FPGA design flow for WARP v1.2. A pcore with an embedded trojan will first need to be designed, the trojan can be in the form of a verilog code. Once the pcore is made using Xilinx System Generator and Matlab, it can then be imported into the WARP FPGA project using Xilinx Platform Studio 10.1.03, thus effectively embedding a trojan in the WARP platform.